Flip chip LEDs are desirable in many applications since they do not use wire bonding. Both electrodes are located on a bottom surface of the LED for direct bonding to metal pads on a submount. Bonding may be accomplished by ultrasonic bonding, solder, conductive adhesive, or other means. Light exits the surface of the LED opposite the electrodes.
In a typical LED flip chip, the epitaxial p-type layer is the bottom layer and is contacted by the bottom anode electrode. A portion of the p-type layer and active layer must be etched away to expose the underside of the epitaxial n-type layer, which allows a connection to the bottom cathode electrode. This etching creates distributed vias through the p-type layer that expose the bottom surface of the n-type layer. The via openings are then insulated, and metal is deposited in the openings for contacting the n-type layer.
Such topography is typically achieved by dry-etch of the semiconductor material (e.g., GaN) in a plasma environment.
The metal contacting the n-type layer and the metal contacting the p-type layer are separated by gaps. Therefore, there is no mechanical support of the brittle semiconductor layers between the metal electrodes.
At the end of wafer level processing, the growth substrates of the LED wafers are thinned and individual dies are formed by singulation. The LED electrodes are then bonded to metal pads on a submount tile, populated by many other LEDs. To prevent breakage of the semiconductor layers, it is known to inject a dielectric, organic based underfill material between the semiconductor layers and the submount. Such an injection process is time-consuming, since the submount tile may support hundreds of LEDs.
To increase light extraction, after the LED electrodes are bonded to the submount tile and the underfill is injected, the growth substrate is removed and thin semiconductor layers, with a typical thickness about 5 microns, are exposed. Such LED structures are referred to as thin film flip chip (TFFC) LEDs. The semiconductor layers are very delicate and susceptible to breakage, and the thinning and the substrate removal process create stresses on the semiconductor layers. Thus, the underfill is required. The submount tile is then singulated, making the mounted devices ready for the next level of packaging.
The underfill material, such as a silicone or epoxy-based composite material (e.g., a molding compound), inherently has some material mismatch with the semiconductor layers, such as coefficient of thermal expansion (CTE) mismatch and Young's modulus mismatch. This leads to delamination or other reliability problems during temperature cycling or other stress conditions.
What is needed is a technique to form a robust TFFC without requiring an underfill for mechanical support.